Design, modelling and analysis of crossbar array for CMOS-based neuromorphic integrated circuits

Abstract

Designing neuromorphic systems using CMOS technology provides a practical and scalable approach to mimic the brain-inspired computation. CMOS technology is widely used as it has mature fabrication processes and higher reliability. One of the key advantages is its energy efficiency, as the circuits can operate in low-power modes, making them ideal for neuromorphic computing, which seeks to replicate the brain’s ability to perform complex tasks with minimal energy consumption. The scalability of this technology allows the development of large-scale neuromorphic systems with compact and high-density transistor integration. This thesis centers on the design of a CMOS-based neuromorphic system, utilizing its inherent advantages. By adopting a CMOS-centric design approach, the work aims to enable efficient integration of emerging synaptic devices. However, despite the advantages of CMOS-based neuromorphic systems, designing large-scale neuromorphic architectures comes with significant challenges. The parasitics of the crossbar array pose a significant challenge in ensuring the accurate multiply and accumulate (MAC) computations within the crossbar. The MAC operation forms the core of the computing module to implement the neuromorphic architecture. The analog MAC blocks are susceptible to the variability effects produced due to the crossbar parasitics, which can result in computation inaccuracies. Therefore, the research focuses on analyzing and modeling the parasitics of the crossbar for different synaptic devices. The parasitics of the crossbar are extracted and analyzed to observe their impact on the performance of the system. A circuit model with all the crossbar-associated parasitics is designed to accurately estimate the system’s efficiency. The designed crossbar-associated parasitic model is adaptable and applicable for crossbars of any size. It enables one to explore and examine how crossbar-associated parasitics would impact the performance of the systems at the schematic level, all without impacting the post-layout simulation outcomes. This approach offers designers a time-saving and efficient means of system design. To train the neuromorphic system for different applications, one must update the weights of the memristive synapses using various methods. The techniques can be broadly categorized into two approaches: ex-situ (offline training) and in-situ (online training), which have both been explored in the research. Thus, different CMOS-based neuromorphic architectures are proposed that are designed for applications such as pattern recognition in which one uses the ex-situ method, and the other is designed using the Hebbian rule. The scalability of the crossbar array is critical for performing complex computation tasks, as large-scale synaptic arrays are required to complete the operations. To address the drawbacks of a 2D neuromorphic IC, such as long routing paths and large die area, 3D IC technology is considered, where the stacking of the crossbar array enhances the system’s scalability. A novel crossbar architecture for 3D neuromorphic IC is proposed where the crossbar array’s area is decreased by approximately 50% and enhancing the architecture’s synaptic density by 50%. Memristors are emerging nanoscale devices that emulate the synaptic behavior of the brain. Various synaptic devices are being used to store the weights to meet the performance requirement of neuro-inspired computing systems. Resistive synapses have been in focus, but recently, capacitive synapses have emerged as a potential candidate for the synaptic device. Therefore, the research analyzes and implements different architectures using resistive and capacitive synapses. The analysis is also done to compare the parasitic effect of both the resistive and capacitive synapses. The system’s performance is analyzed for different applications such as pattern recognition and the MNIST dataset and for checking the effect of parasitics on the spiking pattern of the Izhikevich neuron.