Design of rail-to-rail dynamic comparators and offset calibration for high-speed ADC applications

Abstract

Analog-to-digital converters (ADCs) are essential components in modern electronic systems, bridging the gap between analog signals and digital processing, and are used in various applications, including communication systems, biomedical devices, and neural network architectures. Dynamic comparators being the key building block of ADCs, significantly influence performance metrics of ADC such as speed, power e!ciency, and precision. However, designing dynamic comparators with a wide input common-mode voltage (Vi,cm) range, low energy-delay product (EDP), and e”ective o”set calibration remains a significant challenge. This thesis presents a comprehensive exploration into enhancing the performance of dynamic comparators by addressing key challenges such as limited input common-mode range, kickback noise, and energy e!ciency. The research contributes to both architectural innovation and calibration techniques, resulting in high-speed, low-power, dynamic comparators facilitating rail-to-rail Vi,cm range. The first segment of the thesis addresses architectural enhancements for comparator speed, common-mode insensitivity, and power e!ciency. A low-power, high-speed dynamic comparator architecture, termed the CCDC (Cross-Coupled Dynamic Comparator), is proposed, which incorporates a cross-coupled pair into the pre-amplifier stage followed by a StrongArm latch. This architectural modification enhances both the di”erential and common-mode gain of the pre-amplifier, thereby improving the regeneration process in the latch. The CCDC was fabricated and measured in 180-nm CMOS technology, achieving a measured delay of less than 160 ps, an energy-delay product (EDP) of 81 fJ·ns, and an input-referred noise of 0.8 mV. To demonstrate scalability across technology nodes, the same architecture was also simulated in 65-nm CMOS technology, where simulation results showed a 22% improvement in speed and a 21% reduction in EDP compared to the conventional double-tail comparator. Additionally, the architecture exhibits insensitivity to input common-mode variations, making it robust and suitable for a wide range of high-speed, low-power analog-to-digital conversion applications. To broaden the comparator’s common-mode operating range, the thesis first introduces a rail-to-rail dynamic comparator (RRDC) that merges NMOS and PMOS dynamic pre-amplifiers and activates only one branch at a time through a dedicated clock-gated control. This version is validated by post-layout simulations in 65-nm CMOS at 1 GHz, where it delivers a 17% energy saving while sustaining high-speed operation across the entire 0–Vdd common-mode input range. Building on this idea, thesis also presents an enhanced comparator that combines the benefits of both aforementioned approaches. The cross-coupled RRDC (CC-RRDC) is developed that integrates cross-coupled NMOS and PMOS pre-amplifiers with simplified activation logic, yielding common-mode insensitivity and higher gain. A silicon prototype in 180-nm CMOS confirms a delay below 153 ps, an energy–delay product (EDP) under 77 fJ·ns, and 0.705 mV input-referred noise, while additional simulations in 28-nm CMOS demonstrate scalability to advanced nodes. To further suppress kickback noise without sacrificing speed, the thesis also proposes a modified three-stage rail-to-rail comparator that places parallel NMOS and PMOS pre-amps in front of a strengthened StrongArm latch and inserts an extra gain stage on the NMOS path for noise balancing. This architecture is fabricated and measured in 180-nm CMOS, achieving a delay under 210 ps and an EDP below 86 fJ·ns with markedly improved kickback tolerance. In summary, silicon validation is performed in 180-nm CMOS for the CCDC, CC-RRDC and the three-stage comparator, while 65-nm and 28-nm CMOS results are obtained from detailed post-layout simulations to verify energy e!ciency and process scalability. The second segment of this thesis focuses on o”set reduction—a critical requirement in high-precision applications. A systematic review of various o”set cancellation techniques is provided, including auto-zeroing, chopper stabilization, and self-calibration methods. A calibration-agnostic digital control logic is proposed to facilitate o”set polarity detection and autonomous calibration control. This logic can be integrated with di”erent self-calibration approaches, making it a versatile solution for dynamic comparator o”set correction. Implemented in 180-nm CMOS technology for e”ective transconductance controlled o”set cancellation technique, the input-referred o”set standard deviation is reduced from 2.85 mV to 445 μV, demonstrating its e”ectiveness for high-speed ADCs operating at 1 GHz with a power consumption of 154.6 μW. To further enhance the precision and adaptability of dynamic comparators, the thesis introduces a novel asynchronous bulk-tuned o”set cancellation technique. This method employs a time-domain approach where o”set is sensed through the delay di”erence at the comparator outputs and is minimized using bulk voltage tuning. The technique leverages a dead-zone-free phase detector and a polarity-selective charge pump to achieve energy-e!cient, symmetric calibration. Designed in 65-nm CMOS technology, this technique reduces the o”set standard deviation from 2.183 mV to 33.3 μV, while consuming only 65.8 μW of power and supporting 1 GHz calibration speed in a 2 GHz operating environment, making it suitable for modern, high-speed, high-precision ADC applications. The practical application of the energy-e!cient background o”set calibration by the hybrid of analog and digital sub-ranging approach is also demonstrated through a 6-bit, 1 GS/s partially active flash ADC with background o”set correction. This design eliminates the need for additional foreground calibration cycles, achieving high power e!ciency and operational speed. In conclusion, this thesis significantly contributes to the design of dynamic comparators by addressing critical limitations and proposing robust solutions. The work enhances ADC performance by proposing a comparator design with rail-to-rail operation, improved energy e!ciency, and e”ective o”set calibration. These advancements provide a foundation for future research in mixed-signal circuit design, supporting emerging applications in In-Memory computing, 5G communication systems, and energy-e!cient IoT devices.