Design space exploration of nanoscale interconnects with rough surfaces

Abstract

This paper investigates the effect of surface roughness on interconnect parasitics (RLC per unit length) and performance metrics, such as delay, energy-delay product, bandwidth density, insertion loss and attenuation coefficient of nanoscale on-chip interconnects using 3D EM solver. Our analysis focuses on two industry relevant technology nodes i.e. 13.7 nm and 22 nm. We observe that there is a severe penalty on the performance of interconnects due to surface roughness when analyzed over broadband frequencies. Mandelbrot-Weierstrass (MW) function is used here to define the rough surface profile and the data points obtained from the plot of M-W function are directly used in HFSS for the development of rough conductor interconnect structure. We also present the computational overhead incurred during simulation of rough interconnects.